最終更新:2018-05-24 (木) 17:05:43 (2157d)
EZ-USB FX3 SDK Firmware API/構造体?CyU3PSysClockConfig_t
Top / CyU3PSysClockConfig_t
Clock configuration for FX3 CPU, DMA and register access
構造
型 フィールド 説明 例 CyBool_t setSysClk400 Whether the FX3 master (System) clock is to be set to a frequency greater than 400 MHz. This is required to be set to True if the GPIF is running in 32-bit mode at 100 MHz. uint8_t cpuClkDiv? CPU clock divider from clkSrc. Valid value ranges from 2 - 16 uint8_t dmaClkDiv? DMA clock divider from CPU clock. Valid value ranges from 2 - 16. uint8_t mmioClkDiv? MMIO clock divider from CPU clock. Valid value ranges from 2 - 16. CyBool_t useStandbyClk? Whether the 32 KHz standby clock is supplied. CyU3PSysClockSrc_t clkSrc Clock source for CPU clocking
