最終更新:2016-09-16 (金) 12:47:36 (1394d)  

cpuid
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Dump detailed information about the CPU(s) gathered from the CPUID instruction, and also determine the exact model of CPU(s).

出力

  • CPU 0:
       vendor_id = "GenuineIntel"
       version information (1/eax):
          processor type  = primary processor (0)
          family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
          model           = 0xc (12)
          stepping id     = 0x3 (3)
          extended family = 0x0 (0)
          extended model  = 0x3 (3)
          (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
       miscellaneous (1/ebx):
          process local APIC physical ID = 0x0 (0)
          cpu count                      = 0x4 (4)
          CLFLUSH line size              = 0x8 (8)
          brand index                    = 0x0 (0)
       brand id = 0x00 (0): unknown
       feature information (1/edx):
          x87 FPU on chip                        = true
          virtual-8086 mode enhancement          = true
          debugging extensions                   = true
          page size extensions                   = true
          time stamp counter                     = true
          RDMSR and WRMSR support                = true
          physical address extensions            = true
          machine check exception                = true
          CMPXCHG8B inst.                        = true
          APIC on chip                           = true
          SYSENTER and SYSEXIT                   = true
          memory type range registers            = true
          PTE global bit                         = true
          machine check architecture             = true
          conditional move/compare instruction   = true
          page attribute table                   = true
          page size extension                    = true
          processor serial number                = false
          CLFLUSH instruction                    = true
          debug store                            = false
          thermal monitor and clock ctrl         = false
          MMX Technology                         = true
          FXSAVE/FXRSTOR                         = true
          SSE extensions                         = true
          SSE2 extensions                        = true
          self snoop                             = false
          hyper-threading / multi-core supported = true
          therm. monitor                         = false
          IA64                                   = false
          pending break event                    = false
       feature information (1/ecx):
          PNI/SSE3: Prescott New Instructions     = true
          PCLMULDQ instruction                    = true
          64-bit debug store                      = false
          MONITOR/MWAIT                           = false
          CPL-qualified debug store               = false
          VMX: virtual machine extensions         = false
          SMX: safer mode extensions              = false
          Enhanced Intel SpeedStep Technology     = false
          thermal monitor 2                       = false
          SSSE3 extensions                        = true
          context ID: adaptive or shared L1 data  = false
          FMA instruction                         = false
          CMPXCHG16B instruction                  = true
          xTPR disable                            = false
          perfmon and debug                       = false
          process context identifiers             = false
          direct cache access                     = false
          SSE4.1 extensions                       = true
          SSE4.2 extensions                       = true
          extended xAPIC support                  = true
          MOVBE instruction                       = true
          POPCNT instruction                      = true
          time stamp counter deadline             = false
          AES instruction                         = true
          XSAVE/XSTOR states                      = true
          OS-enabled XSAVE/XSTOR                  = true
          AVX: advanced vector extensions         = true
          F16C half-precision convert instruction = false
          RDRAND instruction                      = true
          hypervisor guest status                 = true
       cache and TLB information (2):
          0x63: data TLB: 1G pages, 4-way, 4 entries
          0x03: data TLB: 4K pages, 4-way, 64 entries
          0x76: instruction TLB: 2M/4M pages, fully, 8 entries
          0xff: cache data is in CPUID 4
          0xb5: instruction TLB: 4K, 8-way, 64 entries
          0xf0: 64 byte prefetching
          0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
       processor serial number: 0003-06C3-0000-0000-0000-0000
       deterministic cache parameters (4):
          --- cache 0 ---
          cache type                           = data cache (1)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 1 ---
          cache type                           = instruction cache (2)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 2 ---
          cache type                           = unified cache (3)
          cache level                          = 0x2 (2)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 511
          --- cache 3 ---
          cache type                           = unified cache (3)
          cache level                          = 0x3 (3)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0xb (11)
          ways of associativity                = 0x6 (6)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = true
          complex cache indexing               = true
          number of sets - 1 (s)               = 8191
       MONITOR/MWAIT (5):
          smallest monitor-line size (bytes)       = 0x0 (0)
          largest monitor-line size (bytes)        = 0x0 (0)
          enum of Monitor-MWAIT exts supported     = false
          supports intrs as break-event for MWAIT  = false
          number of C0 sub C-states using MWAIT    = 0x0 (0)
          number of C1 sub C-states using MWAIT    = 0x0 (0)
          number of C2 sub C-states using MWAIT    = 0x0 (0)
          number of C3 sub C-states using MWAIT    = 0x0 (0)
          number of C4 sub C-states using MWAIT    = 0x0 (0)
          number of C5 sub C-states using MWAIT    = 0x0 (0)
          number of C6 sub C-states using MWAIT    = 0x0 (0)
          number of C7 sub C-states using MWAIT    = 0x0 (0)
       Thermal and Power Management Features (6):
          digital thermometer                     = false
          Intel Turbo Boost Technology            = false
          ARAT always running APIC timer          = false
          PLN power limit notification            = false
          ECMD extended clock modulation duty     = false
          PTM package thermal management          = false
          HWP base registers                      = false
          HWP notification                        = false
          HWP activity window                     = false
          HWP energy performance preference       = false
          HWP package level request               = false
          HDC base registers                      = false
          digital thermometer thresholds          = 0x0 (0)
          ACNT/MCNT supported performance measure = false
          ACNT2 available                         = false
          performance-energy bias capability      = false
       extended feature flags (7):
          FSGSBASE instructions                    = false
          IA32_TSC_ADJUST MSR supported            = false
          BMI instruction                          = false
          HLE hardware lock elision                = false
          AVX2: advanced vector extensions 2       = false
          SMEP supervisor mode exec protection     = false
          BMI2 instructions                        = false
          enhanced REP MOVSB/STOSB                 = false
          INVPCID instruction                      = false
          RTM: restricted transactional memory     = false
          QM: quality of service monitoring        = false
          deprecated FPU CS/DS                     = true
          intel memory protection extensions       = false
          PQE: platform quality of service enforce = false
          AVX512F: AVX-512 foundation instructions = false
          RDSEED instruction                       = false
          ADX instructions                         = false
          SMAP: supervisor mode access prevention  = false
          CLFLUSHOPT instruction                   = false
          Intel processor trace                    = false
          AVX512PF: prefetch instructions          = false
          AVX512ER: exponent & reciprocal instrs   = false
          AVX512CD: conflict detection instrs      = false
          SHA instructions                         = false
          PREFETCHWT1                              = false
          PKU protection keys for user-mode        = false
          OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
       Direct Cache Access Parameters (9):
          PLATFORM_DCA_CAP MSR bits = 0
       Architecture Performance Monitoring Features (0xa/eax):
          version ID                               = 0x0 (0)
          number of counters per logical processor = 0x0 (0)
          bit width of counter                     = 0x0 (0)
          length of EBX bit vector                 = 0x0 (0)
       Architecture Performance Monitoring Features (0xa/ebx):
          core cycle event not available           = false
          instruction retired event not available  = false
          reference cycles event not available     = false
          last-level cache ref event not available = false
          last-level cache miss event not avail    = false
          branch inst retired event not available  = false
          branch mispred retired event not avail   = false
       Architecture Performance Monitoring Features (0xa/edx):
          number of fixed counters    = 0x0 (0)
          bit width of fixed counters = 0x0 (0)
       x2APIC features / processor topology (0xb):
          --- level 0 (thread) ---
          bits to shift APIC ID to get next = 0x0 (0)
          logical processors at this level  = 0x1 (1)
          level number                      = 0x0 (0)
          level type                        = thread (1)
          extended APIC ID                  = 0
          --- level 1 (core) ---
          bits to shift APIC ID to get next = 0x2 (2)
          logical processors at this level  = 0x4 (4)
          level number                      = 0x1 (1)
          level type                        = core (2)
          extended APIC ID                  = 0
       XSAVE features (0xd/0):
          XCR0 lower 32 bits valid bit field mask = 0x00000007
             XCR0 field supported: x87 state      = true
             XCR0 field supported: SSE state      = true
             XCR0 field supported: AVX state      = true
             XCR0 field supported: AVX-512 state  = false
             XCR0 field supported: PKRU state     = false
          bytes required by fields in XCR0        = 0x00000340 (832)
          bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
          XCR0 upper 32 bits valid bit field mask = 0x00000000
       XSAVE features (0xd/1):
          XSAVEOPT instruction                        = false
          XSAVEC instruction                          = false
          XGETBV instruction                          = false
          XSAVES/XRSTORS instructions                 = false
          SAVE area size in bytes                     = 0x00000000 (0)
          IA32_XSS lower 32 bits valid bit field mask = 0x00000000
          IA32_XSS upper 32 bits valid bit field mask = 0x00000000
       AVX/YMM features (0xd/2):
          AVX/YMM save state byte size             = 0x00000100 (256)
          AVX/YMM save state byte offset           = 0x00000240 (576)
          supported in IA32_XSS or XCR0            = XCR0
          64-byte alignment in compacted XSAVE     = false
       hypervisor_id = "KVMKVMKVM   "
       hypervisor features (0x40000001/eax):
          kvmclock available at MSR 0x11          = true
          delays unnecessary for PIO ops          = false
          mmu_op                                  = false
          kvmclock available a MSR 0x4b564d00     = true
          async pf enable available by MSR        = false
          steal clock supported                   = false
          guest EOI optimization enabled          = false
          stable: no guest per-cpu warps expected = true
       extended feature flags (0x80000001/edx):
          SYSCALL and SYSRET instructions        = true
          execution disable                      = true
          1-GB large page support                = false
          RDTSCP                                 = true
          64-bit extensions technology available = true
       Intel feature flags (0x80000001/ecx):
          LAHF/SAHF supported in 64-bit mode     = true
          LZCNT advanced bit manipulation        = true
          3DNow! PREFETCH/PREFETCHW instructions = false
       brand = "Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz"
       L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 data cache information (0x80000005/ecx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L1 instruction cache information (0x80000005/edx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 unified cache information (0x80000006/ecx):
          line size (bytes) = 0x40 (64)
          lines per tag     = 0x0 (0)
          associativity     = 8-way (6)
          size (Kb)         = 0x100 (256)
       L3 cache information (0x80000006/edx):
          line size (bytes)     = 0x0 (0)
          lines per tag         = 0x0 (0)
          associativity         = L2 off (0)
          size (in 512Kb units) = 0x0 (0)
       Advanced Power Management Features (0x80000007/edx):
          temperature sensing diode      = false
          frequency ID (FID) control     = false
          voltage ID (VID) control       = false
          thermal trip (TTP)             = false
          thermal monitor (TM)           = false
          software thermal control (STC) = false
          100 MHz multiplier control     = false
          hardware P-State control       = false
          TscInvariant                   = true
       Physical Address and Linear Address Size (0x80000008/eax):
          maximum physical address bits         = 0x27 (39)
          maximum linear (virtual) address bits = 0x30 (48)
          maximum guest physical address bits   = 0x0 (0)
       Logical CPU cores (0x80000008/ecx):
          number of CPU cores - 1 = 0x0 (0)
          ApicIdCoreIdSize        = 0x0 (0)
       (multi-processing synth): multi-core (c=4)
       (multi-processing method): Intel leaf 0xb
       (APIC widths synth): CORE_width=2 SMT_width=0
       (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
       (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm
    CPU 1:
       vendor_id = "GenuineIntel"
       version information (1/eax):
          processor type  = primary processor (0)
          family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
          model           = 0xc (12)
          stepping id     = 0x3 (3)
          extended family = 0x0 (0)
          extended model  = 0x3 (3)
          (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
       miscellaneous (1/ebx):
          process local APIC physical ID = 0x1 (1)
          cpu count                      = 0x4 (4)
          CLFLUSH line size              = 0x8 (8)
          brand index                    = 0x0 (0)
       brand id = 0x00 (0): unknown
       feature information (1/edx):
          x87 FPU on chip                        = true
          virtual-8086 mode enhancement          = true
          debugging extensions                   = true
          page size extensions                   = true
          time stamp counter                     = true
          RDMSR and WRMSR support                = true
          physical address extensions            = true
          machine check exception                = true
          CMPXCHG8B inst.                        = true
          APIC on chip                           = true
          SYSENTER and SYSEXIT                   = true
          memory type range registers            = true
          PTE global bit                         = true
          machine check architecture             = true
          conditional move/compare instruction   = true
          page attribute table                   = true
          page size extension                    = true
          processor serial number                = false
          CLFLUSH instruction                    = true
          debug store                            = false
          thermal monitor and clock ctrl         = false
          MMX Technology                         = true
          FXSAVE/FXRSTOR                         = true
          SSE extensions                         = true
          SSE2 extensions                        = true
          self snoop                             = false
          hyper-threading / multi-core supported = true
          therm. monitor                         = false
          IA64                                   = false
          pending break event                    = false
       feature information (1/ecx):
          PNI/SSE3: Prescott New Instructions     = true
          PCLMULDQ instruction                    = true
          64-bit debug store                      = false
          MONITOR/MWAIT                           = false
          CPL-qualified debug store               = false
          VMX: virtual machine extensions         = false
          SMX: safer mode extensions              = false
          Enhanced Intel SpeedStep Technology     = false
          thermal monitor 2                       = false
          SSSE3 extensions                        = true
          context ID: adaptive or shared L1 data  = false
          FMA instruction                         = false
          CMPXCHG16B instruction                  = true
          xTPR disable                            = false
          perfmon and debug                       = false
          process context identifiers             = false
          direct cache access                     = false
          SSE4.1 extensions                       = true
          SSE4.2 extensions                       = true
          extended xAPIC support                  = true
          MOVBE instruction                       = true
          POPCNT instruction                      = true
          time stamp counter deadline             = false
          AES instruction                         = true
          XSAVE/XSTOR states                      = true
          OS-enabled XSAVE/XSTOR                  = true
          AVX: advanced vector extensions         = true
          F16C half-precision convert instruction = false
          RDRAND instruction                      = true
          hypervisor guest status                 = true
       cache and TLB information (2):
          0x63: data TLB: 1G pages, 4-way, 4 entries
          0x03: data TLB: 4K pages, 4-way, 64 entries
          0x76: instruction TLB: 2M/4M pages, fully, 8 entries
          0xff: cache data is in CPUID 4
          0xb5: instruction TLB: 4K, 8-way, 64 entries
          0xf0: 64 byte prefetching
          0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
       processor serial number: 0003-06C3-0000-0000-0000-0000
       deterministic cache parameters (4):
          --- cache 0 ---
          cache type                           = data cache (1)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 1 ---
          cache type                           = instruction cache (2)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 2 ---
          cache type                           = unified cache (3)
          cache level                          = 0x2 (2)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 511
          --- cache 3 ---
          cache type                           = unified cache (3)
          cache level                          = 0x3 (3)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0xb (11)
          ways of associativity                = 0x6 (6)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = true
          complex cache indexing               = true
          number of sets - 1 (s)               = 8191
       MONITOR/MWAIT (5):
          smallest monitor-line size (bytes)       = 0x0 (0)
          largest monitor-line size (bytes)        = 0x0 (0)
          enum of Monitor-MWAIT exts supported     = false
          supports intrs as break-event for MWAIT  = false
          number of C0 sub C-states using MWAIT    = 0x0 (0)
          number of C1 sub C-states using MWAIT    = 0x0 (0)
          number of C2 sub C-states using MWAIT    = 0x0 (0)
          number of C3 sub C-states using MWAIT    = 0x0 (0)
          number of C4 sub C-states using MWAIT    = 0x0 (0)
          number of C5 sub C-states using MWAIT    = 0x0 (0)
          number of C6 sub C-states using MWAIT    = 0x0 (0)
          number of C7 sub C-states using MWAIT    = 0x0 (0)
       Thermal and Power Management Features (6):
          digital thermometer                     = false
          Intel Turbo Boost Technology            = false
          ARAT always running APIC timer          = false
          PLN power limit notification            = false
          ECMD extended clock modulation duty     = false
          PTM package thermal management          = false
          HWP base registers                      = false
          HWP notification                        = false
          HWP activity window                     = false
          HWP energy performance preference       = false
          HWP package level request               = false
          HDC base registers                      = false
          digital thermometer thresholds          = 0x0 (0)
          ACNT/MCNT supported performance measure = false
          ACNT2 available                         = false
          performance-energy bias capability      = false
       extended feature flags (7):
          FSGSBASE instructions                    = false
          IA32_TSC_ADJUST MSR supported            = false
          BMI instruction                          = false
          HLE hardware lock elision                = false
          AVX2: advanced vector extensions 2       = false
          SMEP supervisor mode exec protection     = false
          BMI2 instructions                        = false
          enhanced REP MOVSB/STOSB                 = false
          INVPCID instruction                      = false
          RTM: restricted transactional memory     = false
          QM: quality of service monitoring        = false
          deprecated FPU CS/DS                     = true
          intel memory protection extensions       = false
          PQE: platform quality of service enforce = false
          AVX512F: AVX-512 foundation instructions = false
          RDSEED instruction                       = false
          ADX instructions                         = false
          SMAP: supervisor mode access prevention  = false
          CLFLUSHOPT instruction                   = false
          Intel processor trace                    = false
          AVX512PF: prefetch instructions          = false
          AVX512ER: exponent & reciprocal instrs   = false
          AVX512CD: conflict detection instrs      = false
          SHA instructions                         = false
          PREFETCHWT1                              = false
          PKU protection keys for user-mode        = false
          OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
       Direct Cache Access Parameters (9):
          PLATFORM_DCA_CAP MSR bits = 0
       Architecture Performance Monitoring Features (0xa/eax):
          version ID                               = 0x0 (0)
          number of counters per logical processor = 0x0 (0)
          bit width of counter                     = 0x0 (0)
          length of EBX bit vector                 = 0x0 (0)
       Architecture Performance Monitoring Features (0xa/ebx):
          core cycle event not available           = false
          instruction retired event not available  = false
          reference cycles event not available     = false
          last-level cache ref event not available = false
          last-level cache miss event not avail    = false
          branch inst retired event not available  = false
          branch mispred retired event not avail   = false
       Architecture Performance Monitoring Features (0xa/edx):
          number of fixed counters    = 0x0 (0)
          bit width of fixed counters = 0x0 (0)
       x2APIC features / processor topology (0xb):
          --- level 0 (thread) ---
          bits to shift APIC ID to get next = 0x0 (0)
          logical processors at this level  = 0x1 (1)
          level number                      = 0x0 (0)
          level type                        = thread (1)
          extended APIC ID                  = 1
          --- level 1 (core) ---
          bits to shift APIC ID to get next = 0x2 (2)
          logical processors at this level  = 0x4 (4)
          level number                      = 0x1 (1)
          level type                        = core (2)
          extended APIC ID                  = 1
       XSAVE features (0xd/0):
          XCR0 lower 32 bits valid bit field mask = 0x00000007
             XCR0 field supported: x87 state      = true
             XCR0 field supported: SSE state      = true
             XCR0 field supported: AVX state      = true
             XCR0 field supported: AVX-512 state  = false
             XCR0 field supported: PKRU state     = false
          bytes required by fields in XCR0        = 0x00000340 (832)
          bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
          XCR0 upper 32 bits valid bit field mask = 0x00000000
       XSAVE features (0xd/1):
          XSAVEOPT instruction                        = false
          XSAVEC instruction                          = false
          XGETBV instruction                          = false
          XSAVES/XRSTORS instructions                 = false
          SAVE area size in bytes                     = 0x00000000 (0)
          IA32_XSS lower 32 bits valid bit field mask = 0x00000000
          IA32_XSS upper 32 bits valid bit field mask = 0x00000000
       AVX/YMM features (0xd/2):
          AVX/YMM save state byte size             = 0x00000100 (256)
          AVX/YMM save state byte offset           = 0x00000240 (576)
          supported in IA32_XSS or XCR0            = XCR0
          64-byte alignment in compacted XSAVE     = false
       hypervisor_id = "KVMKVMKVM   "
       hypervisor features (0x40000001/eax):
          kvmclock available at MSR 0x11          = true
          delays unnecessary for PIO ops          = false
          mmu_op                                  = false
          kvmclock available a MSR 0x4b564d00     = true
          async pf enable available by MSR        = false
          steal clock supported                   = false
          guest EOI optimization enabled          = false
          stable: no guest per-cpu warps expected = true
       extended feature flags (0x80000001/edx):
          SYSCALL and SYSRET instructions        = true
          execution disable                      = true
          1-GB large page support                = false
          RDTSCP                                 = true
          64-bit extensions technology available = true
       Intel feature flags (0x80000001/ecx):
          LAHF/SAHF supported in 64-bit mode     = true
          LZCNT advanced bit manipulation        = true
          3DNow! PREFETCH/PREFETCHW instructions = false
       brand = "Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz"
       L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 data cache information (0x80000005/ecx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L1 instruction cache information (0x80000005/edx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 unified cache information (0x80000006/ecx):
          line size (bytes) = 0x40 (64)
          lines per tag     = 0x0 (0)
          associativity     = 8-way (6)
          size (Kb)         = 0x100 (256)
       L3 cache information (0x80000006/edx):
          line size (bytes)     = 0x0 (0)
          lines per tag         = 0x0 (0)
          associativity         = L2 off (0)
          size (in 512Kb units) = 0x0 (0)
       Advanced Power Management Features (0x80000007/edx):
          temperature sensing diode      = false
          frequency ID (FID) control     = false
          voltage ID (VID) control       = false
          thermal trip (TTP)             = false
          thermal monitor (TM)           = false
          software thermal control (STC) = false
          100 MHz multiplier control     = false
          hardware P-State control       = false
          TscInvariant                   = true
       Physical Address and Linear Address Size (0x80000008/eax):
          maximum physical address bits         = 0x27 (39)
          maximum linear (virtual) address bits = 0x30 (48)
          maximum guest physical address bits   = 0x0 (0)
       Logical CPU cores (0x80000008/ecx):
          number of CPU cores - 1 = 0x0 (0)
          ApicIdCoreIdSize        = 0x0 (0)
       (multi-processing synth): multi-core (c=4)
       (multi-processing method): Intel leaf 0xb
       (APIC widths synth): CORE_width=2 SMT_width=0
       (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
       (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm
    CPU 2:
       vendor_id = "GenuineIntel"
       version information (1/eax):
          processor type  = primary processor (0)
          family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
          model           = 0xc (12)
          stepping id     = 0x3 (3)
          extended family = 0x0 (0)
          extended model  = 0x3 (3)
          (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
       miscellaneous (1/ebx):
          process local APIC physical ID = 0x2 (2)
          cpu count                      = 0x4 (4)
          CLFLUSH line size              = 0x8 (8)
          brand index                    = 0x0 (0)
       brand id = 0x00 (0): unknown
       feature information (1/edx):
          x87 FPU on chip                        = true
          virtual-8086 mode enhancement          = true
          debugging extensions                   = true
          page size extensions                   = true
          time stamp counter                     = true
          RDMSR and WRMSR support                = true
          physical address extensions            = true
          machine check exception                = true
          CMPXCHG8B inst.                        = true
          APIC on chip                           = true
          SYSENTER and SYSEXIT                   = true
          memory type range registers            = true
          PTE global bit                         = true
          machine check architecture             = true
          conditional move/compare instruction   = true
          page attribute table                   = true
          page size extension                    = true
          processor serial number                = false
          CLFLUSH instruction                    = true
          debug store                            = false
          thermal monitor and clock ctrl         = false
          MMX Technology                         = true
          FXSAVE/FXRSTOR                         = true
          SSE extensions                         = true
          SSE2 extensions                        = true
          self snoop                             = false
          hyper-threading / multi-core supported = true
          therm. monitor                         = false
          IA64                                   = false
          pending break event                    = false
       feature information (1/ecx):
          PNI/SSE3: Prescott New Instructions     = true
          PCLMULDQ instruction                    = true
          64-bit debug store                      = false
          MONITOR/MWAIT                           = false
          CPL-qualified debug store               = false
          VMX: virtual machine extensions         = false
          SMX: safer mode extensions              = false
          Enhanced Intel SpeedStep Technology     = false
          thermal monitor 2                       = false
          SSSE3 extensions                        = true
          context ID: adaptive or shared L1 data  = false
          FMA instruction                         = false
          CMPXCHG16B instruction                  = true
          xTPR disable                            = false
          perfmon and debug                       = false
          process context identifiers             = false
          direct cache access                     = false
          SSE4.1 extensions                       = true
          SSE4.2 extensions                       = true
          extended xAPIC support                  = true
          MOVBE instruction                       = true
          POPCNT instruction                      = true
          time stamp counter deadline             = false
          AES instruction                         = true
          XSAVE/XSTOR states                      = true
          OS-enabled XSAVE/XSTOR                  = true
          AVX: advanced vector extensions         = true
          F16C half-precision convert instruction = false
          RDRAND instruction                      = true
          hypervisor guest status                 = true
       cache and TLB information (2):
          0x63: data TLB: 1G pages, 4-way, 4 entries
          0x03: data TLB: 4K pages, 4-way, 64 entries
          0x76: instruction TLB: 2M/4M pages, fully, 8 entries
          0xff: cache data is in CPUID 4
          0xb5: instruction TLB: 4K, 8-way, 64 entries
          0xf0: 64 byte prefetching
          0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
       processor serial number: 0003-06C3-0000-0000-0000-0000
       deterministic cache parameters (4):
          --- cache 0 ---
          cache type                           = data cache (1)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 1 ---
          cache type                           = instruction cache (2)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 2 ---
          cache type                           = unified cache (3)
          cache level                          = 0x2 (2)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 511
          --- cache 3 ---
          cache type                           = unified cache (3)
          cache level                          = 0x3 (3)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0xb (11)
          ways of associativity                = 0x6 (6)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = true
          complex cache indexing               = true
          number of sets - 1 (s)               = 8191
       MONITOR/MWAIT (5):
          smallest monitor-line size (bytes)       = 0x0 (0)
          largest monitor-line size (bytes)        = 0x0 (0)
          enum of Monitor-MWAIT exts supported     = false
          supports intrs as break-event for MWAIT  = false
          number of C0 sub C-states using MWAIT    = 0x0 (0)
          number of C1 sub C-states using MWAIT    = 0x0 (0)
          number of C2 sub C-states using MWAIT    = 0x0 (0)
          number of C3 sub C-states using MWAIT    = 0x0 (0)
          number of C4 sub C-states using MWAIT    = 0x0 (0)
          number of C5 sub C-states using MWAIT    = 0x0 (0)
          number of C6 sub C-states using MWAIT    = 0x0 (0)
          number of C7 sub C-states using MWAIT    = 0x0 (0)
       Thermal and Power Management Features (6):
          digital thermometer                     = false
          Intel Turbo Boost Technology            = false
          ARAT always running APIC timer          = false
          PLN power limit notification            = false
          ECMD extended clock modulation duty     = false
          PTM package thermal management          = false
          HWP base registers                      = false
          HWP notification                        = false
          HWP activity window                     = false
          HWP energy performance preference       = false
          HWP package level request               = false
          HDC base registers                      = false
          digital thermometer thresholds          = 0x0 (0)
          ACNT/MCNT supported performance measure = false
          ACNT2 available                         = false
          performance-energy bias capability      = false
       extended feature flags (7):
          FSGSBASE instructions                    = false
          IA32_TSC_ADJUST MSR supported            = false
          BMI instruction                          = false
          HLE hardware lock elision                = false
          AVX2: advanced vector extensions 2       = false
          SMEP supervisor mode exec protection     = false
          BMI2 instructions                        = false
          enhanced REP MOVSB/STOSB                 = false
          INVPCID instruction                      = false
          RTM: restricted transactional memory     = false
          QM: quality of service monitoring        = false
          deprecated FPU CS/DS                     = true
          intel memory protection extensions       = false
          PQE: platform quality of service enforce = false
          AVX512F: AVX-512 foundation instructions = false
          RDSEED instruction                       = false
          ADX instructions                         = false
          SMAP: supervisor mode access prevention  = false
          CLFLUSHOPT instruction                   = false
          Intel processor trace                    = false
          AVX512PF: prefetch instructions          = false
          AVX512ER: exponent & reciprocal instrs   = false
          AVX512CD: conflict detection instrs      = false
          SHA instructions                         = false
          PREFETCHWT1                              = false
          PKU protection keys for user-mode        = false
          OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
       Direct Cache Access Parameters (9):
          PLATFORM_DCA_CAP MSR bits = 0
       Architecture Performance Monitoring Features (0xa/eax):
          version ID                               = 0x0 (0)
          number of counters per logical processor = 0x0 (0)
          bit width of counter                     = 0x0 (0)
          length of EBX bit vector                 = 0x0 (0)
       Architecture Performance Monitoring Features (0xa/ebx):
          core cycle event not available           = false
          instruction retired event not available  = false
          reference cycles event not available     = false
          last-level cache ref event not available = false
          last-level cache miss event not avail    = false
          branch inst retired event not available  = false
          branch mispred retired event not avail   = false
       Architecture Performance Monitoring Features (0xa/edx):
          number of fixed counters    = 0x0 (0)
          bit width of fixed counters = 0x0 (0)
       x2APIC features / processor topology (0xb):
          --- level 0 (thread) ---
          bits to shift APIC ID to get next = 0x0 (0)
          logical processors at this level  = 0x1 (1)
          level number                      = 0x0 (0)
          level type                        = thread (1)
          extended APIC ID                  = 2
          --- level 1 (core) ---
          bits to shift APIC ID to get next = 0x2 (2)
          logical processors at this level  = 0x4 (4)
          level number                      = 0x1 (1)
          level type                        = core (2)
          extended APIC ID                  = 2
       XSAVE features (0xd/0):
          XCR0 lower 32 bits valid bit field mask = 0x00000007
             XCR0 field supported: x87 state      = true
             XCR0 field supported: SSE state      = true
             XCR0 field supported: AVX state      = true
             XCR0 field supported: AVX-512 state  = false
             XCR0 field supported: PKRU state     = false
          bytes required by fields in XCR0        = 0x00000340 (832)
          bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
          XCR0 upper 32 bits valid bit field mask = 0x00000000
       XSAVE features (0xd/1):
          XSAVEOPT instruction                        = false
          XSAVEC instruction                          = false
          XGETBV instruction                          = false
          XSAVES/XRSTORS instructions                 = false
          SAVE area size in bytes                     = 0x00000000 (0)
          IA32_XSS lower 32 bits valid bit field mask = 0x00000000
          IA32_XSS upper 32 bits valid bit field mask = 0x00000000
       AVX/YMM features (0xd/2):
          AVX/YMM save state byte size             = 0x00000100 (256)
          AVX/YMM save state byte offset           = 0x00000240 (576)
          supported in IA32_XSS or XCR0            = XCR0
          64-byte alignment in compacted XSAVE     = false
       hypervisor_id = "KVMKVMKVM   "
       hypervisor features (0x40000001/eax):
          kvmclock available at MSR 0x11          = true
          delays unnecessary for PIO ops          = false
          mmu_op                                  = false
          kvmclock available a MSR 0x4b564d00     = true
          async pf enable available by MSR        = false
          steal clock supported                   = false
          guest EOI optimization enabled          = false
          stable: no guest per-cpu warps expected = true
       extended feature flags (0x80000001/edx):
          SYSCALL and SYSRET instructions        = true
          execution disable                      = true
          1-GB large page support                = false
          RDTSCP                                 = true
          64-bit extensions technology available = true
       Intel feature flags (0x80000001/ecx):
          LAHF/SAHF supported in 64-bit mode     = true
          LZCNT advanced bit manipulation        = true
          3DNow! PREFETCH/PREFETCHW instructions = false
       brand = "Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz"
       L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 data cache information (0x80000005/ecx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L1 instruction cache information (0x80000005/edx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 unified cache information (0x80000006/ecx):
          line size (bytes) = 0x40 (64)
          lines per tag     = 0x0 (0)
          associativity     = 8-way (6)
          size (Kb)         = 0x100 (256)
       L3 cache information (0x80000006/edx):
          line size (bytes)     = 0x0 (0)
          lines per tag         = 0x0 (0)
          associativity         = L2 off (0)
          size (in 512Kb units) = 0x0 (0)
       Advanced Power Management Features (0x80000007/edx):
          temperature sensing diode      = false
          frequency ID (FID) control     = false
          voltage ID (VID) control       = false
          thermal trip (TTP)             = false
          thermal monitor (TM)           = false
          software thermal control (STC) = false
          100 MHz multiplier control     = false
          hardware P-State control       = false
          TscInvariant                   = true
       Physical Address and Linear Address Size (0x80000008/eax):
          maximum physical address bits         = 0x27 (39)
          maximum linear (virtual) address bits = 0x30 (48)
          maximum guest physical address bits   = 0x0 (0)
       Logical CPU cores (0x80000008/ecx):
          number of CPU cores - 1 = 0x0 (0)
          ApicIdCoreIdSize        = 0x0 (0)
       (multi-processing synth): multi-core (c=4)
       (multi-processing method): Intel leaf 0xb
       (APIC widths synth): CORE_width=2 SMT_width=0
       (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
       (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm
    CPU 3:
       vendor_id = "GenuineIntel"
       version information (1/eax):
          processor type  = primary processor (0)
          family          = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
          model           = 0xc (12)
          stepping id     = 0x3 (3)
          extended family = 0x0 (0)
          extended model  = 0x3 (3)
          (simple synth)  = Intel Core i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / Mobile Core i5-4000 / Mobile Core i7-4000 / Pentium G3000 / Celeron G1800 / Mobile Pentium 3500U / Mobile Celeron 2900U / Xeon E3-1200 v3 (Mobile M) (Haswell), 22nm
       miscellaneous (1/ebx):
          process local APIC physical ID = 0x3 (3)
          cpu count                      = 0x4 (4)
          CLFLUSH line size              = 0x8 (8)
          brand index                    = 0x0 (0)
       brand id = 0x00 (0): unknown
       feature information (1/edx):
          x87 FPU on chip                        = true
          virtual-8086 mode enhancement          = true
          debugging extensions                   = true
          page size extensions                   = true
          time stamp counter                     = true
          RDMSR and WRMSR support                = true
          physical address extensions            = true
          machine check exception                = true
          CMPXCHG8B inst.                        = true
          APIC on chip                           = true
          SYSENTER and SYSEXIT                   = true
          memory type range registers            = true
          PTE global bit                         = true
          machine check architecture             = true
          conditional move/compare instruction   = true
          page attribute table                   = true
          page size extension                    = true
          processor serial number                = false
          CLFLUSH instruction                    = true
          debug store                            = false
          thermal monitor and clock ctrl         = false
          MMX Technology                         = true
          FXSAVE/FXRSTOR                         = true
          SSE extensions                         = true
          SSE2 extensions                        = true
          self snoop                             = false
          hyper-threading / multi-core supported = true
          therm. monitor                         = false
          IA64                                   = false
          pending break event                    = false
       feature information (1/ecx):
          PNI/SSE3: Prescott New Instructions     = true
          PCLMULDQ instruction                    = true
          64-bit debug store                      = false
          MONITOR/MWAIT                           = false
          CPL-qualified debug store               = false
          VMX: virtual machine extensions         = false
          SMX: safer mode extensions              = false
          Enhanced Intel SpeedStep Technology     = false
          thermal monitor 2                       = false
          SSSE3 extensions                        = true
          context ID: adaptive or shared L1 data  = false
          FMA instruction                         = false
          CMPXCHG16B instruction                  = true
          xTPR disable                            = false
          perfmon and debug                       = false
          process context identifiers             = false
          direct cache access                     = false
          SSE4.1 extensions                       = true
          SSE4.2 extensions                       = true
          extended xAPIC support                  = true
          MOVBE instruction                       = true
          POPCNT instruction                      = true
          time stamp counter deadline             = false
          AES instruction                         = true
          XSAVE/XSTOR states                      = true
          OS-enabled XSAVE/XSTOR                  = true
          AVX: advanced vector extensions         = true
          F16C half-precision convert instruction = false
          RDRAND instruction                      = true
          hypervisor guest status                 = true
       cache and TLB information (2):
          0x63: data TLB: 1G pages, 4-way, 4 entries
          0x03: data TLB: 4K pages, 4-way, 64 entries
          0x76: instruction TLB: 2M/4M pages, fully, 8 entries
          0xff: cache data is in CPUID 4
          0xb5: instruction TLB: 4K, 8-way, 64 entries
          0xf0: 64 byte prefetching
          0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
       processor serial number: 0003-06C3-0000-0000-0000-0000
       deterministic cache parameters (4):
          --- cache 0 ---
          cache type                           = data cache (1)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 1 ---
          cache type                           = instruction cache (2)
          cache level                          = 0x1 (1)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 63
          --- cache 2 ---
          cache type                           = unified cache (3)
          cache level                          = 0x2 (2)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0x7 (7)
          ways of associativity                = 0x0 (0)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = false
          complex cache indexing               = false
          number of sets - 1 (s)               = 511
          --- cache 3 ---
          cache type                           = unified cache (3)
          cache level                          = 0x3 (3)
          self-initializing cache level        = true
          fully associative cache              = false
          extra threads sharing this cache     = 0x0 (0)
          extra processor cores on this die    = 0x3 (3)
          system coherency line size           = 0x3f (63)
          physical line partitions             = 0x0 (0)
          ways of associativity                = 0xb (11)
          ways of associativity                = 0x6 (6)
          WBINVD/INVD behavior on lower caches = false
          inclusive to lower caches            = true
          complex cache indexing               = true
          number of sets - 1 (s)               = 8191
       MONITOR/MWAIT (5):
          smallest monitor-line size (bytes)       = 0x0 (0)
          largest monitor-line size (bytes)        = 0x0 (0)
          enum of Monitor-MWAIT exts supported     = false
          supports intrs as break-event for MWAIT  = false
          number of C0 sub C-states using MWAIT    = 0x0 (0)
          number of C1 sub C-states using MWAIT    = 0x0 (0)
          number of C2 sub C-states using MWAIT    = 0x0 (0)
          number of C3 sub C-states using MWAIT    = 0x0 (0)
          number of C4 sub C-states using MWAIT    = 0x0 (0)
          number of C5 sub C-states using MWAIT    = 0x0 (0)
          number of C6 sub C-states using MWAIT    = 0x0 (0)
          number of C7 sub C-states using MWAIT    = 0x0 (0)
       Thermal and Power Management Features (6):
          digital thermometer                     = false
          Intel Turbo Boost Technology            = false
          ARAT always running APIC timer          = false
          PLN power limit notification            = false
          ECMD extended clock modulation duty     = false
          PTM package thermal management          = false
          HWP base registers                      = false
          HWP notification                        = false
          HWP activity window                     = false
          HWP energy performance preference       = false
          HWP package level request               = false
          HDC base registers                      = false
          digital thermometer thresholds          = 0x0 (0)
          ACNT/MCNT supported performance measure = false
          ACNT2 available                         = false
          performance-energy bias capability      = false
       extended feature flags (7):
          FSGSBASE instructions                    = false
          IA32_TSC_ADJUST MSR supported            = false
          BMI instruction                          = false
          HLE hardware lock elision                = false
          AVX2: advanced vector extensions 2       = false
          SMEP supervisor mode exec protection     = false
          BMI2 instructions                        = false
          enhanced REP MOVSB/STOSB                 = false
          INVPCID instruction                      = false
          RTM: restricted transactional memory     = false
          QM: quality of service monitoring        = false
          deprecated FPU CS/DS                     = true
          intel memory protection extensions       = false
          PQE: platform quality of service enforce = false
          AVX512F: AVX-512 foundation instructions = false
          RDSEED instruction                       = false
          ADX instructions                         = false
          SMAP: supervisor mode access prevention  = false
          CLFLUSHOPT instruction                   = false
          Intel processor trace                    = false
          AVX512PF: prefetch instructions          = false
          AVX512ER: exponent & reciprocal instrs   = false
          AVX512CD: conflict detection instrs      = false
          SHA instructions                         = false
          PREFETCHWT1                              = false
          PKU protection keys for user-mode        = false
          OSPKE CR4.PKE and RDPKRU/WRPKRU          = false
       Direct Cache Access Parameters (9):
          PLATFORM_DCA_CAP MSR bits = 0
       Architecture Performance Monitoring Features (0xa/eax):
          version ID                               = 0x0 (0)
          number of counters per logical processor = 0x0 (0)
          bit width of counter                     = 0x0 (0)
          length of EBX bit vector                 = 0x0 (0)
       Architecture Performance Monitoring Features (0xa/ebx):
          core cycle event not available           = false
          instruction retired event not available  = false
          reference cycles event not available     = false
          last-level cache ref event not available = false
          last-level cache miss event not avail    = false
          branch inst retired event not available  = false
          branch mispred retired event not avail   = false
       Architecture Performance Monitoring Features (0xa/edx):
          number of fixed counters    = 0x0 (0)
          bit width of fixed counters = 0x0 (0)
       x2APIC features / processor topology (0xb):
          --- level 0 (thread) ---
          bits to shift APIC ID to get next = 0x0 (0)
          logical processors at this level  = 0x1 (1)
          level number                      = 0x0 (0)
          level type                        = thread (1)
          extended APIC ID                  = 3
          --- level 1 (core) ---
          bits to shift APIC ID to get next = 0x2 (2)
          logical processors at this level  = 0x4 (4)
          level number                      = 0x1 (1)
          level type                        = core (2)
          extended APIC ID                  = 3
       XSAVE features (0xd/0):
          XCR0 lower 32 bits valid bit field mask = 0x00000007
             XCR0 field supported: x87 state      = true
             XCR0 field supported: SSE state      = true
             XCR0 field supported: AVX state      = true
             XCR0 field supported: AVX-512 state  = false
             XCR0 field supported: PKRU state     = false
          bytes required by fields in XCR0        = 0x00000340 (832)
          bytes required by XSAVE/XRSTOR area     = 0x00000340 (832)
          XCR0 upper 32 bits valid bit field mask = 0x00000000
       XSAVE features (0xd/1):
          XSAVEOPT instruction                        = false
          XSAVEC instruction                          = false
          XGETBV instruction                          = false
          XSAVES/XRSTORS instructions                 = false
          SAVE area size in bytes                     = 0x00000000 (0)
          IA32_XSS lower 32 bits valid bit field mask = 0x00000000
          IA32_XSS upper 32 bits valid bit field mask = 0x00000000
       AVX/YMM features (0xd/2):
          AVX/YMM save state byte size             = 0x00000100 (256)
          AVX/YMM save state byte offset           = 0x00000240 (576)
          supported in IA32_XSS or XCR0            = XCR0
          64-byte alignment in compacted XSAVE     = false
       hypervisor_id = "KVMKVMKVM   "
       hypervisor features (0x40000001/eax):
          kvmclock available at MSR 0x11          = true
          delays unnecessary for PIO ops          = false
          mmu_op                                  = false
          kvmclock available a MSR 0x4b564d00     = true
          async pf enable available by MSR        = false
          steal clock supported                   = false
          guest EOI optimization enabled          = false
          stable: no guest per-cpu warps expected = true
       extended feature flags (0x80000001/edx):
          SYSCALL and SYSRET instructions        = true
          execution disable                      = true
          1-GB large page support                = false
          RDTSCP                                 = true
          64-bit extensions technology available = true
       Intel feature flags (0x80000001/ecx):
          LAHF/SAHF supported in 64-bit mode     = true
          LZCNT advanced bit manipulation        = true
          3DNow! PREFETCH/PREFETCHW instructions = false
       brand = "Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz"
       L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = 0x0 (0)
          data # entries            = 0x0 (0)
          data associativity        = 0x0 (0)
       L1 data cache information (0x80000005/ecx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L1 instruction cache information (0x80000005/edx):
          line size (bytes) = 0x0 (0)
          lines per tag     = 0x0 (0)
          associativity     = 0x0 (0)
          size (Kb)         = 0x0 (0)
       L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
          instruction # entries     = 0x0 (0)
          instruction associativity = L2 off (0)
          data # entries            = 0x0 (0)
          data associativity        = L2 off (0)
       L2 unified cache information (0x80000006/ecx):
          line size (bytes) = 0x40 (64)
          lines per tag     = 0x0 (0)
          associativity     = 8-way (6)
          size (Kb)         = 0x100 (256)
       L3 cache information (0x80000006/edx):
          line size (bytes)     = 0x0 (0)
          lines per tag         = 0x0 (0)
          associativity         = L2 off (0)
          size (in 512Kb units) = 0x0 (0)
       Advanced Power Management Features (0x80000007/edx):
          temperature sensing diode      = false
          frequency ID (FID) control     = false
          voltage ID (VID) control       = false
          thermal trip (TTP)             = false
          thermal monitor (TM)           = false
          software thermal control (STC) = false
          100 MHz multiplier control     = false
          hardware P-State control       = false
          TscInvariant                   = true
       Physical Address and Linear Address Size (0x80000008/eax):
          maximum physical address bits         = 0x27 (39)
          maximum linear (virtual) address bits = 0x30 (48)
          maximum guest physical address bits   = 0x0 (0)
       Logical CPU cores (0x80000008/ecx):
          number of CPU cores - 1 = 0x0 (0)
          ApicIdCoreIdSize        = 0x0 (0)
       (multi-processing synth): multi-core (c=4)
       (multi-processing method): Intel leaf 0xb
       (APIC widths synth): CORE_width=2 SMT_width=0
       (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
       (synth) = Intel Core i3-4000 / i5-4000 / i7-4000 / Mobile Core i3-4000 / i5-4000 / i7-4000 (Haswell), 22nm