最終更新:2022-03-18 (金) 10:35:29 (1032d)
Universal Serial Bus Specification Revision 2.0
Top / Universal Serial Bus Specification Revision 2.0
Revision 2.0
April 27, 2000
章
内容
Contents
CHAPTER 1 INTRODUCTION
- 1.1 Motivation
- 1.2 Objective of the Specification
- 1.3 Scope of the Document
- 1.4 USB Product Compliance
- 1.5 Document Organization
CHAPTER 2 TERMS AND ABBREVIATIONS
CHAPTER 3 BACKGROUND
- 3.1 Goals for the Universal Serial Bus
- 3.2 Taxonomy of Application Space
- 3.3 Feature List
CHAPTER 4 ARCHITECTURAL OVERVIEW
- 4.1 USB System Description
- 4.1.1 Bus Topology
- 4.2 Physical Interface
- 4.2.1 Electrical
- 4.2.2 Mechanical
- 4.3 Power
- 4.3.1 Power Distribution
- 4.3.2 Power Management
- 4.4 Bus Protocol
- 4.5 Robustness
- 4.5.1 Error Detection
- 4.5.2 Error Handling
- 4.6 System Configuration
- 4.6.1 Attachment of USB Devices
- 4.6.2 Removal of USB Devices
- 4.6.3 Bus Enumeration
- 4.7 Data Flow Types
- 4.7.1 Control Transfers
- 4.7.2 Bulk Transfers
- 4.7.3 Interrupt Transfers
- 4.7.4 Isochronous Transfers
- 4.7.5 Allocating USB Bandwidth
- 4.8 USB Devices
- 4.8.1 Device Characterizations
- 4.8.2 Device Descriptions
- 4.9 USB Host: Hardware and Software
- 4.10 Architectural Extensions
CHAPTER 5 USB DATA FLOW MODEL
- 5.1 Implementer Viewpoints
- 5.2 Bus Topology
- 5.2.1 USB Host
- 5.2.2 USB Devices
- 5.2.3 Physical Bus Topology
- 5.2.4 Logical Bus Topology
- 5.2.5 Client Software-to-function Relationship
- 5.3 USB Communication Flow
- 5.3.1 Device Endpoints
- 5.3.2 Pipes
- 5.3.3 Frames and Microframes
- 5.4 Transfer Types
- 5.4.1 Table Calculation Examples
- 5.5 Control Transfers
- 5.5.1 Control Transfer Data Format
- 5.5.2 Control Transfer Direction
- 5.5.3 Control Transfer Packet Size Constraints
- 5.5.4 Control Transfer Bus Access Constraints
- 5.5.5 Control Transfer Data Sequences
- 5.6 Isochronous Transfers
- 5.6.1 Isochronous Transfer Data Format
- 5.6.2 Isochronous Transfer Direction
- 5.6.3 Isochronous Transfer Packet Size Constraints
- 5.6.4 Isochronous Transfer Bus Access Constraints
- 5.6.5 Isochronous Transfer Data Sequences
- 5.7 Interrupt Transfers
- 5.7.1 Interrupt Transfer Data Format
- 5.7.2 Interrupt Transfer Direction
- 5.7.3 Interrupt Transfer Packet Size Constraints
- 5.7.4 Interrupt Transfer Bus Access Constraints
- 5.7.5 Interrupt Transfer Data Sequences
- 5.8 Bulk Transfers
- 5.8.1 Bulk Transfer Data Format
- 5.8.2 Bulk Transfer Direction
- 5.8.3 Bulk Transfer Packet Size Constraints
- 5.8.4 Bulk Transfer Bus Access Constraints
- 5.8.5 Bulk Transfer Data Sequences
- 5.9 High-Speed, High Bandwidth Endpoints
- 5.9.1 High Bandwidth Interrupt Endpoints
- 5.9.2 High Bandwidth Isochronous Endpoints
- 5.10 Split Transactions
- 5.11 Bus Access for Transfers
- 5.11.1 Transfer Management
- 5.11.2 Transaction Tracking
- 5.11.3 Calculating Bus Transaction Times
- 5.11.4 Calculating Buffer Sizes in Functions and Software
- 5.11.5 Bus Bandwidth Reclamation
- 5.12 Special Considerations for Isochronous Transfers
- 5.12.1 Example Non-USB Isochronous Application
- 5.12.2 USB Clock Model
- 5.12.3 Clock Synchronization
- 5.12.4 Isochronous Devices
- 5.12.5 Data Prebuffering
- 5.12.6 SOF Tracking
- 5.12.7 Error Handling
- 5.12.8 Buffering for Rate Matching
CHAPTER 6 MECHANICAL
- 6.1 Architectural Overview
- 6.2 Keyed Connector Protocol
- 6.3 Cable
- 6.4 Cable Assembly
- 6.4.1 Standard Detachable Cable Assemblies
- 6.4.2 High-/full-speed Captive Cable Assemblies
- 6.4.3 Low-speed Captive Cable Assemblies
- 6.4.4 Prohibited Cable Assemblies
- 6.5 Connector Mechanical Configuration and Material Requirements
- 6.5.1 USB Icon Location
- 6.5.2 USB Connector Termination Data
- 6.5.3 Series “A” and Series “B” Receptacles
- 6.5.4 Series “A” and Series “B” Plugs
- 6.6 Cable Mechanical Configuration and Material Requirements
- 6.6.1 Description
- 6.6.2 Construction
- 6.6.3 Electrical Characteristics
- 6.1.4 Cable Environmental Characteristics
- 6.1.5 Listing
- 6.7 Electrical, Mechanical, and Environmental Compliance Standards
- 6.7.1 Applicable Documents
- 6.8 USB Grounding
- 6.9 PCB Reference Drawings
CHAPTER 7 ELECTRICAL
- 7.1 Signaling
- 7.1.1 USB Driver Characteristics
- 7.1.2 Data Signal Rise and Fall, Eye Patterns
- 7.1.3 Cable Skew
- 7.1.4 Receiver Characteristics
- 7.1.5 Device Speed Identification
- 7.1.6 Input Characteristics
- 7.1.7 Signaling Levels
- 7.1.8 Data Encoding/Decoding
- 7.1.9 Bit Stuffing
- 7.1.10 Sync Pattern
- 7.1.11 Data Signaling Rate
- 7.1.12 Frame Interval
- 7.1.13 Data Source Signaling
- 7.1.14 Hub Signaling Timings
- 7.1.15 Receiver Data Jitter
- 7.1.16 Cable Delay
- 7.1.17 Cable Attenuation
- 7.1.18 Bus Turn-around Time and Inter-packet Delay
- 7.1.19 Maximum End-to-end Signal Delay
- 7.1.20 Test Mode Support
- 7.2 Power Distribution
- 7.2.1 Classes of Devices
- 7.2.2 Voltage Drop Budget
- 7.2.3 Power Control During Suspend/Resume
- 7.2.4 Dynamic Attach and Detach
- 7.3 Physical Layer
- 7.3.1 Regulatory Requirements
- 7.3.2 Bus Timing/Electrical Characteristics
- 7.3.3 Timing Waveforms
CHAPTER 8 PROTOCOL LAYER
- 8.1 Byte/Bit Ordering
- 8.2 SYNC Field
- 8.3 Packet Field Formats
- 8.3.1 Packet Identifier Field
- 8.3.2 Address Fields
- 8.3.3 Frame Number Field
- 8.3.4 Data Field
- 8.3.5 Cyclic Redundancy Checks
- 8.4 Packet Formats
- 8.4.1 Token Packets
- 8.4.2 Split Transaction Special Token Packets
- 8.4.3 Start-of-Frame Packets
- 8.4.4 Data Packets
- 8.4.5 Handshake Packets
- 8.4.6 Handshake Responses
- 8.5 Transaction Packet Sequences
- 8.5.1 NAK Limiting via Ping Flow Control
- 8.5.2 Bulk Transactions
- 8.5.3 Control Transfers
- 8.5.4 Interrupt Transactions
- 8.5.5 Isochronous Transactions
- 8.6 Data Toggle Synchronization and Retry
- 8.6.1 Initialization via SETUP Token
- 8.6.2 Successful Data Transactions
- 8.6.3 Data Corrupted or Not Accepted
- 8.6.4 Corrupted ACK Handshake
- 8.6.5 Low-speed Transactions
- 8.7 Error Detection and Recovery
- 8.7.1 Packet Error Categories
- 8.7.2 Bus Turn-around Timing
- 8.7.3 False EOPs
- 8.7.4 Babble and Loss of Activity Recovery
CHAPTER 9 USB DEVICE FRAMEWORK
- 9.1 USB Device States
- 9.1.1 Visible Device States
- 9.1.2 Bus Enumeration
- 9.2 Generic USB Device Operations
- 9.2.1 Dynamic Attachment and Removal
- 9.2.2 Address Assignment
- 9.2.3 Configuration
- 9.2.4 Data Transfer
- 9.2.5 Power Management
- 9.2.6 Request Processing
- 9.2.7 Request Error
- 9.3 USB Device Requests
- 9.3.1 bmRequestType
- 9.3.2 bRequest
- 9.3.3 wValue
- 9.3.4 wIndex
- 9.3.5 wLength
- 9.4 Standard Device Requests
- 9.4.1 Clear Feature
- 9.4.2 Get Configuration
- 9.4.3 Get Descriptor
- 9.4.4 Get Interface
- 9.4.5 Get Status
- 9.4.6 Set Address
- 9.4.7 Set Configuration
- 9.4.8 Set Descriptor
- 9.4.9 Set Feature
- 9.4.10 Set Interface
- 9.4.11 Synch Frame
- 9.5 Descriptors (USB/ディスクリプタ)
- 9.6 Standard USB Descriptor Definitions
- 9.6.1 Device (デバイスディスクリプタ)
- 9.6.2 Device_Qualifier
- 9.6.3 Configuration (コンフィグレーションディスクリプタ)
- 9.6.4 Other_Speed_Configuration
- 9.6.5 Interface (インターフェイスディスクリプタ)
- 9.6.6 Endpoint (エンドポイントディスクリプタ)
- 9.6.7 String (ストリングディスクリプタ)
- 9.7 Device Class Definitions
- 9.7.1 Descriptors
- 9.7.2 Interface(s) and Endpoint Usage
- 9.7.3 Requests
CHAPTER 10 USB HOST: HARDWARE AND SOFTWARE
- 10.1 Overview of the USB Host
- 10.1.1 Overview
- 10.1.2 Control Mechanisms
- 10.1.3 Data Flow
- 10.1.4 Collecting Status and Activity Statistics
- 10.1.5 Electrical Interface Considerations
- 10.2 Host Controller Requirements
- 10.2.1 State Handling
- 10.2.2 Serializer/Deserializer
- 10.2.3 Frame and Microframe Generation
- 10.2.4 Data Processing
- 10.2.5 Protocol Engine
- 10.2.6 Transmission Error Handling
- 10.2.7 Remote Wakeup
- 10.2.8 Root Hub
- 10.2.9 Host System Interface
- 10.3 Overview of Software Mechanisms
- 10.3.1 Device Configuration
- 10.3.2 Resource Management
- 10.3.3 Data Transfers
- 10.3.4 Common Data Definitions
- 10.4 Host Controller Driver
- 10.5 Universal Serial Bus Driver
- 10.5.1 USBD Overview
- 10.5.2 USBD Command Mechanism Requirements
- 10.5.3 USBD Pipe Mechanisms
- 10.5.4 Managing the USB via the USBD Mechanisms
- 10.5.5 Passing USB Preboot Control to the Operating System
- 10.6 Operating System Environment Guides
CHAPTER 11 HUB SPECIFICATION
- USBハブ
- 11.1 Overview
- 11.1.1 Hub Architecture
- 11.1.2 Hub Connectivity
- 11.2 Hub Frame/Microframe Timer
- 11.2.1 High-speed Microframe Timer Range
- 11.2.2 Full-speed Frame Timer Range
- 11.2.3 Frame/Microframe Timer Synchronization
- 11.2.4 Microframe Jitter Related to Frame Jitter
- 11.2.5 EOF1 and EOF2 Timing Points
- 11.3 Host Behavior at End-of-Frame
- 11.3.1 Full-/low-speed Latest Host Packet
- 11.3.2 Full-/low-speed Packet Nullification
- 11.3.3 Full-/low-speed Transaction Completion Prediction
- 11.4 Internal Port
- 11.4.1 Inactive
- 11.4.2 Suspend Delay
- 11.4.3 Full Suspend (Fsus)
- 11.4.4 Generate Resume (GResume)
- 11.5 Downstream Facing Ports
- 11.5.1 Downstream Facing Port State Descriptions
- 11.5.2 Disconnect Detect Timer
- 11.5.3 Port Indicator
- 11.6 Upstream Facing Port
- 11.6.1 Full-speed
- 11.6.2 High-speed
- 11.6.3 Receiver
- 11.6.4 Transmitter
- 11.7 Hub Repeater
- 11.7.1 High-speed Packet Connectivity
- 11.7.2 Hub Repeater State Machine
- 11.7.3 Wait for Start of Packet from Upstream Port (WFSOPFU)
- 11.7.4 Wait for End of Packet from Upstream Port (WFEOPFU)
- 11.7.5 Wait for Start of Packet (WFSOP)
- 11.7.6 Wait for End of Packet (WFEOP)
- 11.8 Bus State Evaluation
- 11.8.1 Port Error
- 11.8.2 Speed Detection
- 11.8.3 Collision
- 11.8.4 Low-speed Port Behavior
- 11.9 Suspend and Resume
- 11.10 Hub Reset Behavior
- 11.11 Hub Port Power Control
- 11.11.1 Multiple Gangs
- 11.12 Hub Controller
- 11.12.1 Endpoint Organization
- 11.12.2 Hub Information Architecture and Operation
- 11.12.3 Port Change Information Processing
- 11.12.4 Hub and Port Status Change Bitmap
- 11.12.5 Over-current Reporting and Recovery
- 11.12.6 Enumeration Handling
- 11.13 Hub Configuration
- 11.14 Transaction Translator
- 11.14.1 Overview
- 11.14.2 Transaction Translator Scheduling
- 11.15 Split Transaction Notation Information
- 11.16 Common Split Transaction State Machines
- 11.16.1 Host Controller State Machine
- 11.16.2 Transaction Translator State Machine
- 11.17 Bulk/Control Transaction Translation Overview
- 11.17.1 Bulk/Control Split Transaction Sequences
- 11.17.2 Bulk/Control Split Transaction State Machines
- 11.17.3 Bulk/Control Sequencing
- 11.17.4 Bulk/Control Buffering Requirements
- 11.17.5 Other Bulk/Control Details
- 11.18 Periodic Split Transaction Pipelining and Buffer Management
- 11.18.1 Best Case Full-Speed Budget
- 11.18.2 TT Microframe Pipeline
- 11.18.3 Generation of Full-speed Frames
- 11.18.4 Host Split Transaction Scheduling Requirements
- 11.18.5 TT Response Generation
- 11.18.6 TT Periodic Transaction Handling Requirements
- 11.18.7 TT Transaction Tracking
- 11.18.8 TT Complete-split Transaction State Searching
- 11.19 Approximate TT Buffer Space Required
- 11.20 Interrupt Transaction Translation Overview
- 11.20.1 Interrupt Split Transaction Sequences
- 11.20.2 Interrupt Split Transaction State Machines
- 11.20.3 Interrupt OUT Sequencing
- 11.20.4 Interrupt IN Sequencing
- 11.21 Isochronous Transaction Translation Overview
- 11.21.1 Isochronous Split Transaction Sequences
- 11.21.2 Isochronous Split Transaction State Machines
- 11.21.3 Isochronous OUT Sequencing
- 11.21.4 Isochronous IN Sequencing
- 11.22 TT Error Handling
- 11.22.1 Loss of TT Synchronization With HS SOFs
- 11.22.2 TT Frame and Microframe Timer Synchronization Requirements
- 11.23 Descriptors
- 11.23.1 Standard Descriptors for Hub Class
- 11.23.2 Class-specific Descriptors
- 11.24 Requests
- 11.24.1 Standard Requests
- 11.24.2 Class-specific Requests
